1. Field of the Invention
The present invention relates to an I2C bus controlling method. More particularly, it relates to an I2C bus controlling method for use in modules for optical communications.
2. Description of Related Art
There have been provided, as serial buses for use in optical communication modules, a management data input/output bus (referred to as an MDIO bus from here on) and an inter integrated circuit bus (referred to as an I2C bus from here on). An IC for communication control (referred to as a PHY unit from here on), which can be disposed in optical communication modules, is provided with a non-volatile register (referred to as an NVR register from here on), a register for digital optical monitoring (referred to as a DOM register from here on), and a register for MDIO. While the PHY unit is connected, via an MDIO bus, to a host that controls the PHY unit, it is also connected, via an I2C bus, to a nonvolatile external storage (referred to as an EEPROM from here on), such as an EEPROM, a flash memory, an IC (referred to as an MCU from here on) having an operation function and peripheral functions, or the like.
Conventionally, as an initializing method for use with optical communication modules (referred to as modules from here on), there are two types of RESET: hardware RESET (referred to as HW-RESET from here on) of initializing the PHY unit by sending a RESET signal to each IC of the PHY unit, and software RESET (referred to as SW-RESET from here on) of initializing the PHY unit in response to a RESET command from the host.
When starting the module, the host outputs an HW-RESET signal to the module so as to reset the PHY unit. The PHY unit reads NVR data required for initial setting (referred to as NVR data from here on) from the EEPROM (or MCU) via the I2C bus after being started. The Host needs to carry out SW-RESET by sending a RESET command to the module after carrying out HW-RESET. As a result, the PHY unit is reset again, and the supply of a serial clock signal (referred to an SCL signal from here on) via the I2C bus is stopped.
Communications via the I2C bus are carried out in synchronization with the SCL signal. A serial data signal (referred to as an SDA signal from here on) is also synchronized with the SCL signal. To be more specific, when the SCL signal has a low level, the SDA signal changes, whereas when the SCL signal has a high level, the SDA signal does not change.
When SW-RESET occurs while data at a corresponding address from the EEPROM (or MCU) are piggybacked onto the SDA signal and the data are outputted via the I2C bus, the supply of the SCL signal from the PHY unit via the I2C bus is stopped with the SCL signal being at a high state according to the I2C bus standards, and therefore the SDA signal does not change, either. Although the PHY unit generates an internal signal for resetting itself when SW-RESET is started, the internal signal cannot be applied to the EEPROM (or MCU). As a result, the EEPROM (or MCU) stops while being in a state in which it is using the I2C bus.
There has been provided a common equipment protection circuit having a monitoring circuit for generating an initialization completion signal at the time of completion of initialization of two or more pieces of common equipment which are connected to a system bus, the initialization being carried out at the time of reset of a system, and a processor module locking circuit for generating a signal for disabling a processor module group connected to the above-mentioned system bus to access the system bus when a main power supply is switched on, and for generating a signal for enabling the processor module group to access the system bus, although the common equipment protection circuit is not related to I2C buses (refer to, for example, patent reference 1).
[Patent Reference 1] JP, 62-150414, A
A problem with the related art I2C bus controlling method which is executed as mentioned above is that if above-mentioned SW-RESET occurs when the PHY unit is reading NVR data from the EEPROM (or MCU) mounted in the module, using the I2C bus or the like at the time of startup of the system, the EEPROM (or MCU) stops while it is in the middle of carrying out communications via the I2C bus and falls into an inoperative (i.e., hangup) state, and it becomes impossible to release this state.
While the disclosure of patent reference 1 is mainly related to the occurrence of HW-RESET, I2C buses differs from conventional buses in many ways, such as in that two or more pieces of equipment are connected to one another by using an SCL signal and an SDA signal so that they can exchange data with one another, a communications partner is specified using the SCL signal, and a multi-master function is provided. Therefore, patent reference 1 cannot be applied to I2C buses.